1. Field of the Invention
The invention relates generally to integrated circuit clocking and, more specifically to clock signal distribution in integrated circuits.
2. Description of Related Art
An issue facing the integrated circuit industry today is the problem of distributing clock signals throughout an integrated circuit die with low clock skew. Clock skew is the difference in arrival times of clock edges to different parts of the chip. Synchronous digital logic requires precise clocks for latching data. Ideal synchronous logic relies on clocks arriving simultaneously to all the circuits. Clock skew reduces the maximum frequency of the circuit as the circuit must be designed for the worst case skew to operate reliably.
The challenge facing integrated circuit designers is to insure that the clock switches at exactly the same time throughout the chip so that each circuit is kept in step to avoid delays that can cause chip failure. In prior art global clock distribution networks, clock skew caused by signal routing is typically controlled by the use of hierarchical H-trees. FIG. 1 is a diagram illustrating such a hierarchical H-tree clock distribution network 101 that is implemented in high-speed integrated circuits to reduce the clock skew effect. As shown in FIG. 1, a clock driver 103 is used to drive H-tree network 101 at center node 105. It is appreciated that clock driver 103 is typically a very large driver in order to provide sufficient drive to Htree network 101, which typically has a large capacitance in complex, high-speed integrated circuits as will be described below. As observed in FIG. 1, the clock paths of the "H" formed between nodes 107, 109, 111, and 113 have equal length between center node 105 and each of the peripheral points of the "H" at nodes 107, 109, 111, and 113, respectively. Therefore, assuming a uniform propagation delay of a clock signal per unit length of the H-tree network 101, there should be no clock skew between the clock signal supplied to nodes 107, 109, 111, and 113 from clock driver 103.
FIG. 1 further illustrates H-tree network 101 taken to another hierarchical level with an "H" coupled to each respective peripheral node of the first level "H". Accordingly, every peripheral node 115 is an equal distance from node 107. Every peripheral node 117 is an equal distance from node 109. Every peripheral node 119 is an equal distance from node 111. Finally, every peripheral node 121 is an equal distance from 113. Thus, the clock paths from all nodes labeled 115, 117, 119, and 121 are an equal distance from clock driver 103 and therefore should have no clock skew between them (assuming a uniform propagation delay) since the clock delay from clock driver 103 should be equal at all peripheral nodes of the H-tree network 101. Thus, each node 115, 117, 119, and 121 can be configured to act as a receiving station for a clock signal and service the clocking requirements of an area of the integrated circuit near the node with negligible clock skew with reference to other similarly configured nodes of the H-tree network.
As described, the H-tree propagation delay of a clock signal per unit length of the network may be controlled by placing every peripheral node an equal distance from clock driver 103. However, the propagation delay of a clock signal because of length or distance of the paths traveled by the signal is only one ingredient that leads to skew. Another equally important ingredient is the consistency of speed of the signal as it traverses the path. One component that affects the speed of this signal is the resistance of the metal. Metal layers, such as Aluminum (Al), have an inherent resistivity that is a property of the metal, but the actual resistance a signal encounters can be affected by the thickness of the metal layer, because resistance is inversely proportional to layer thickness. In general, however, clock metal layer thickness is approximately 1.5 microns (.mu.m) making the resistance of the metal fairly consistent or predictable in most integrated circuits.
The consistency of the speed of the signal in prior art clock distribution networks also depends generally on the impedance the signal encounters as it travels from the clock driver to the receiving station or clocked circuit. For a modern integrated circuit, there could be five or more metal interconnect layers on a chip, each interconnect layer separated from the other by a dielectric layer. The conventional clock network, such as H-tree network 101 overlays this structure. The clock network is laid out on a dielectric preferably overlying a ground plane metal. The speed of the signals along the path of the network is governed by the capacitance created in the dielectric between the clock network and the ground plane metal. Further, this capacitance is not consistent or uniform across the chip. This is so because the topography of a given chip gives rise to local variations, such as variations in the thickness of interlayer dielectric material relative to the underlying layer of metal and the presence of or absence of underlying metal layers. Interlayer dielectric thickness is important relative to the next level of metal. Further, the capacitive coupling from nearby switching lines adds to or subtracts from the clock signal development. The described variations inherent in a chip illustrate that the capacitance is dynamic, and therefore it is difficult to control the impedance encountered by the clock network, and thus the signal speed. In general, there is an inherent raw skew in the H-tree network due to this variation in signal speed of at least 150-200 pico seconds.
One effort to eliminate the skew caused by delays in signal speed is through the use of variable delay buffers (also referred to as deskew buffers) at the ends of the H-tree. The additional intentional skew introduced by these special buffers is controlled by a carefully distributed reference clock whose skew is made small. In this way, the main clocks at each of the endpoints of the H-tree are synchronized to the low skew reference clock. Although this scheme is very effective in reducing clock skew, the deskew buffers can cause additional jitter on the main clock due to the presence of any power supply noise internal to the chip. Hence, reduced skew is traded for increased jitter.
A second effort to eliminate or reduce timing skew is to use copper (Cu) as the interconnect metal forming the clock distribution. Since the consistency of the signal propagation is a function of the product of the capacitance and resistance, reducing the resistance reduces the sensitivity of the signal propagation to variations in the capacitance. The resistance of copper interconnect can be up to 50% lower than that of conventional Al-0.5% Cu. However, as the clock rate keeps climbing, even the resistance improvements provided by copper metallization may not be sufficient to control skew.
Even with sophisticated clock network configurations like the H-tree network, deskew circuits, and copper metallization, integrated circuits typically have a skew budget built into them that allows the circuits to tolerate a certain amount of skew after which point the processing speed must be reduced. A general rule of thumb for a skew budget is a clock skew of 10% of the clock frequency.
In addition to clock skew and jitter, the clock distribution on the chip consumes valuable routing resources on integrated circuits that could be better used for signals and improved signal routability. As noted above, a preferred clock network routing is on top of a chip above a ground plane metal layer and separated by a dielectric layer. This preferred routing requires two layers of metal.
In addition to integrated circuit die area, the global clock distribution networks utilized today consume an increasing amount of power. If the total capacitance of the clock network is C, the power dissipated is CV.sup.2 f where V is the supply voltage and f is the frequency. The global clock distribution network on today's high-speed integrated circuit chips typically accounts for approximately 10% of the chip power.
The clock distribution network on a chip must be compatible with the chip package. The conventional packaging of a chip is illustrated in FIG. 2. FIG. 2 is an illustration of a chip 205 packaged in a wire bond package 211. As shown in FIG. 2, wire bonds 203 for example, gold wire bonds, are used to connect package 211 and chip 205.
Another type of packaging, is the Controlled Collapse Chip Connection (C4) packaged chips (sometimes referred to as flip-chip). FIG. 3 is an illustration of a C4 package 251. C4 is the packaging of choice for high frequency chips as it provides high density, low inductance connections using ball bonds 253 between chip 255 and package 261 by eliminating the high inductance bond wires that are in wire bond packages.